The present invention relates to a semiconductor memory device, and more particularly to a data read control circuit of a static random access memory.
Essential elements for reading/writing data from/to a static random access memory include a read control circuit for receiving a read enable signal to read data and a write control circuit for receiving a write enable signal to write data. As semiconductor memory devices have become highly integrated and operating voltages have been reduced, reliability can be improved only if the read control circuit and write control circuit carry out accurate operations at high speeds.
CMOS random access memory devices include static random access memories (SRAM) and dynamic random access memories (DRAM), etc. The static random access memory uses a latch circuit for storing data, and the dynamic random access memory stores charge in a capacitor. More particularly, the structure of a static memory cell in a static random access memory device is a latch structure composed of two crossly connected inverters. That is, an output of one inverter becomes an input of the other inverter. In a write mode, data (1 or 0) is loaded on bit lines, and is stored into a memory cell by selecting a word line. To read data, after both bit lines are pre-charged, the word line is selected.
FIG. 1 illustrates a static random access memory according to the prior art.
The static random access memory shown in FIG. 1 has precharge control circuit 110 for precharging bit lines BL and BL, memory cell 120 for storing predetermined data and being assigned by an X-address through word line WL connected to NMOS transistors 15 and 30, read control circuit 100 connected to bit line BL for receiving read enable signal RE to control a read operation when data is read from memory cell 120, and write control circuit 130 for receiving data supplied from a data bus in conjunction with write enable signal WE used to control a write operation when data is written to memory cell 120. Read control circuit 100 is composed of an inverter controlled by read enable signal RE for shaping the level of the outputted data. Also, the static random access memory device shown in FIG. 1 has Y-address generation circuit 95 for selecting bit line selection transistors, i.e., NMOS transistors 35 and 40 when data is read/written from/to memory cell 120. Memory cell 120 has a latch structure composed of inverters 20 and 25 and, accordingly, nodes A and B are set to data in different logic states. Write control circuit 130 has PMOS transistor 45 whose drain and source terminal are respectively connected to node N3 and power supply voltage VCC, PMOS transistor 60 whose drain and source terminals are respectively connected to node N4 and power supply voltage VCC, PMOS transistors 50 and 55 whose drain and gate terminals are crossly connected, and pull-down NMOS transistors 75 and 80 connected between drain terminals of PMOS transistors 50 and 55 and ground voltage VSS. The gate terminal of NMOS transistor 75 is connected to an output terminal of NOR gate 70, which receives data supplied from the data bus and the write enable signal inverted by inverter 65. The gate terminal of NMOS transistor 80 is connected to an output terminal of NOR gate 85, which receives an output signal of NOR gate 70 and the write enable signal inverted by inverter 65.
In the static random access device shown in FIG. 1, when the device is not in a data read mode or a data write mode, then read enable signal RE and write enable signal WE are at logic "low" states, respectively. When the read enable signal RE and the write enable signal WE keep are at "low" states, respectively, a precharge signal PCGB is at a logic "low" state. Accordingly, PMOS transistors 5 and 10 of precharge circuit 110 are turned on, and PMOS transistors 45 and 60 of write control circuit 130 are also turned on. Since the source terminals of PMOS transistors 5 and 10 of precharge circuit 110 and PMOS transistors 45 and 60 of write control circuit 130 are respectively connected to the power supply voltage, nodes N1, N2, N3 and N4 are precharged to the power supply voltage level by receiving the logic "low" state precharge signal PCGB.
If the read enable signal RE goes to a logic "high" state, i.e., if a read mode is carried out, precharge signal PCGB also becomes a logic "high" state. Accordingly, PMOS transistors 5 and 10 of precharge circuit 110 and PMOS transistors 45 and 60 of write control circuit 130 are respectively turned off. Accordingly, the potentials of nodes N1 and N2 are changed by data supplied from the memory cell 120.
Also, if write enable signal WE goes to a logic "high" state, i.e., if a write mode is carried out, precharge signal PCGB also becomes a logic "high" state. Accordingly, PMOS transistors 5 and 10 of precharge circuit 110 and PMOS transistors 45 and 60 of write control circuit 130 are respectively turned off. Accordingly, the potentials of nodes N3 and N4 are changed by data supplied from the write control circuit.
Meanwhile, those skilled in the art will readily understand that the write enable signal WE and the read enable signal RE do not go to the logic "high" state at the same time.
Here, X-address signals X0, . . . , Xi supplied from X-address generation circuit 90 and Y-address signals Y0, . . . , Yi supplied from Y-address generation circuit 95 maintain logic "low" states, if precharge signal PCGB is in a logic "low" state. However, if precharge signal PCGB goes to a logic "high" state, one X-address signal among X-address signals X0, . . . , Xi supplied from X-address generation circuit 90 and one Y-address signal among Y-address signals Y0, . . . , Yi supplied from Y-address generation circuit 95 become logic "high" states, respectively, and accordingly, only the memory cell assigned by the corresponding address signal performs the read/write operation.
The operation of an access memory according to the prior art will now be described in detail with reference to FIGS. 1 and 2.
First, the case of writing data to memory cell 120 will be described. In writing data to memory cell 120, write enable signal WE is at a logic "high" state. After nodes N1, N2, N3 and N4 are precharged to the power supply voltage level if write enable signal WE is enabled to a logic "high" state then the random access memory device goes into a write mode. When data transmitted from the data bus is at a logic "high" state, the output signal of NOR gate 70 becomes a logic "low" state and, accordingly, NMOS transistor 75 is turned off. At this time, the output signal of NOR gate 85 becomes a logic "high" state, so that NMOS transistor 80 is turned on. The potential of node N4 goes to a logic "low" state by the turn-on of NMOS transistor 80 and, accordingly, PMOS transistor 50 is turned on. The node N3 goes to a logic "high" state by the turn-on of PMOS transistor 50, so that PMOS transistor 55 is turned off. As described above, in this case one X-address signal among X-address signals X0, . . . , Xi supplied from X-address generation circuit 90 and one Y-address signal among Y-address signals supplied from Y-address generation circuit 95 become logic "high" states, respectively and, accordingly, a memory cell is assigned by the corresponding address signal. Accordingly, NMOS transistors 35 and 40 are respectively turned on, so that the logic "high" state signal having the power supply voltage level set at node N3 is dropped by threshold voltage Vth of NMOS transistor 35 and is transmitted to node N1. However, since node N1 is previously precharged to the power supply voltage level, the potential of node N1 becomes VCC-Vth after a predetermined time period elapses, as shown in the timing diagram of FIG. 2. At this time, since the potential of node N4 of write control circuit 130 keeps a logic "low" state, even passing NMOS transistor 40 does not generate a voltage drop. Accordingly, data of logic "low" state is constantly transmitted to node N2. Since logic "low" state data set at node N2 is transmitted to node B of memory cell 120 and the structure of memory cell 120 is a latch composed of inverters 20 and 25, node A is set to logic "high" state data. As a result, even if potential VCC-Vth set at node N1 is transferred to node A, node A is set to the full power supply voltage level by the operation of inverters 20 and 25. Accordingly, an accurate write operation can be performed with the memory cell 120.
When data transmitted from the data bus is in a logic "low" state, the output signal of NOR gate 70 goes to a logic "high" state and, accordingly, NMOS transistor 75 is turned on. At this time, the output signal of NOR gate 85 goes to a logic "low" state, so that NMOS transistor 80 is turned off. The potential of node N3 goes to a logic "low" state by the turn-on of NMOS transistor 75 and, accordingly, PMOS transistor 55 is turned on. The node N4 goes to a logic "high" state by the turn-on of PMOS transistor 55, so that PMOS transistor 50 is turned off. As described above, in this case one X-address signal among X-address signals supplied from X-address generation circuit 90 and one Y-address signal among Y-address signals supplied from Y-address generation circuit 95 become logic "high" states, respectively, and accordingly, a memory cell is assigned by the corresponding address signal. Accordingly, since NMOS transistors 35 and 40 are respectively turned on, the logic "high" state signal having the power supply voltage level set at node N4 is dropped by the threshold voltage Vth of NMOS transistor 40 and is transmitted to node N2. However, since node N2 is previously precharged to the power supply voltage level, the potential of node N2 becomes VCC-Vth after a predetermined time period elapses. At this time, since the potential of node N3 of write control circuit 130 is at a logic "low" state, even passing NMOS transistor 35 does not generate a voltage drop. Accordingly, the logic "low" state data is constantly transmitted to node N1. Accordingly, since logic "low" state data set at node N1 is transmitted to node A of memory cell 120, and the structure of memory cell 120 is a latch composed of inverters 20 and 25, node B is set to logic "high" state data. As a result, even if the potential VCC-Vth set at node N2 is transferred to node B, the full power supply voltage level is set to node B by the operation of inverters 20 and 25. Accordingly, an accurate write operation can be performed with memory cell 120.
The case of reading data from memory cell 120 will now be described. In reading data from memory cell 120, read enable signal RE is at a logic "high" state. After nodes N1, N2, N3 and N4 are precharged to the power supply voltage level by precharge signal PCGB of logic "low" state, if the read enable signal WE is enabled to a logic "high" state, one X-address signal among X-address signals X0, . . . , Xi supplied from the X-address generation circuit 90 and one Y-address signal among Y-address signals Y0, . . . , Yi supplied from Y-address generation circuit 95 become logic "high" states, respectively. Accordingly, data from memory cell 120 are respectively supplied to node N1 and N2 by the corresponding address signals.
First, when node A of memory cell 120 is at a logic "high" state of the power supply voltage level and node B is at a logic "low" state of the ground voltage level, data having the potential VCC-Vth dropped by the threshold voltage Vth of NMOS transistor 15 is set to node N1 by the turn-on of NMOS transistors 15 and 30, and data of logic "low" state is set to node N2. At this time, since node N1 is previously charged to the power supply voltage level, the potential VCC-Vth is set at node N1 after a predetermined time period elapses. Meanwhile, after node N3 of write control circuit 130 is charged to the logic "high" state power supply voltage level, it has a potential VCC-Vth if read enable signal RE goes to a logic "high" state and a predetermined time period elapses. Accordingly, after the logic "low" state signal set at node N4 is supplied to read control circuit 100, logic "high" state data is supplied to the data bus.
When node A of memory cell 120 is at a logic "low" state of the ground voltage level and node B is at a logic "high" state of the power supply voltage level, NMOS transistors 15 and 30 are turned on, thereby setting data of logic "low" state to node N1 and setting to node N2 data having the potential VCC-Vth dropped by the threshold voltage Vth of NMOS transistor 30. At this time, since node N2 is previously precharged to the power supply voltage level, node N2 is set to the potential VCC-Vth after a predetermined time period elapses, as shown in the timing diagram of FIG. 3. Meanwhile, after node N4 of write control circuit 130 is previously charged to a logic "high" state of power supply voltage level, it has the potential VCC-Vth, as shown in the timing diagram of FIG. 3, if read enable signal RE gpes to a logic "high" state and a predetermined time period elapses. Accordingly, the signal having the voltage level VCC-Vth set at node N4 is fed to read control circuit 100 and then logic "low" state data is supplied to the data bus. Here, if a read time, i.e., a time of enabling read enable signal RE to a logic "high" state, is lengthened, the potential set at node N4 is set to a potential VCC-Vth. At this time, when the potential of the supply voltage is in the high state, i.e., if the voltage over the logic threshold voltage corresponding to the inverter of read control circuit 100 is supplied, an accurate read operation is performed. Meanwhile, even if the potential of the supply voltage is low and the interval of keeping read enable signal RE at a logic "high" state is short, i.e., even if the read operation is ended before node N4 of write control circuit 130 is discharged to the voltage level VCC-Vth, the read operation is accurately performed.
However, in the random access memory according to the prior art shown in FIG. 1, when the potential of the supply voltage is low and the interval of keeping the read enable signal RE a logic "high" state is lengthened, i.e., if the read operation is performed in a low-voltage and low-frequency region, the voltage at node N4 is discharged to VCC-Vth during the interval of keeping read enable signal RE in a logic "high" state, thereby inaccurately setting the logic threshold voltage corresponding to the inverter of read control circuit 100. Accordingly, there is the problem of generating false operation when reading data, since the operation of inverter of the read control circuit 100 becomes unstable.